High-κ dielectric

由于二氧化硅(SiO2)具有易制性 (Manufacturability),且能减少厚度以持续改善晶体管效能,因此过去40余年来,处理器厂商均采用二氧化硅做为制作闸极电介质的材料。

当英特尔导入65纳米制造工艺时,虽已全力将二氧化硅闸极电介质厚度降低至1.2纳米,相当于5层原子,但由于晶体管缩至原子大小的尺寸时,耗电和散热亦会同时增加,产生电流浪费和不必要的热能,因此若继续采用目前材料,进一步减少厚度,闸极电介质的漏电情况势将会明显攀升,令缩小晶体管技术遭遇极限。

为解决此关键问题,英特尔正规划改用较厚的High-K材料(铪hafnium元素为基础的物质)作为闸极电介质,取代沿用至今已超过40年的二氧化硅,此举也成功使漏电量降低10倍以上。

另与上一代65纳米技术相较,英特尔的45纳米制程令晶体管密度提升近2倍,得以增加处理器的晶体管总数或缩小处理器体积,令产品较对手更具竞争力,此外,晶体管开关动作所需电力更低,耗电量减少近30%,内部连接线 (interconnects) 采用铜线搭配 Low-k电介质,顺利提升效能并降低耗电量,开关动作速度约加快 20%。

From Wikipedia:

The term high-κ dielectric refers to a material with a high dielectric constant κ (as compared to silicon dioxide). High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon dioxide gate dielectric or another dielectric layer of a device. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore’s Law. Sometimes these materials are called “high-k” instead of “high-κ” (high kappa).

Need for high-κ materials

Silicon dioxide (SiO2) has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance.[_disputeddiscuss_] As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the associated leakage effects.

First principles

The gate oxide in a MOSFET can be modeled as a parallel plate capacitor. Ignoring quantum mechanical and depletion effects from the Si substrate and gate, thecapacitance _C_ of this parallel plate capacitor is given by

C=frac{kappavarepsilon_{0}A}{t}

Conventional silicon dioxide gate dielectric structure compared to a potential high-k dielectric structure

Cross-section of an N channelMOSFET transistor showing the gate oxide dielectric

Where

Since leakage limitation constrains further reduction of _t_, an alternative method to increase gate capacitance is alter κ by replacing silicon dioxide with a high-κ material. In such a scenario, a thicker gate oxide layer might be used which can reduce the leakage current flowing through the structure as well as improving the gate dielectric reliability.

Gate capacitance impact on drive current[edit]

The drain current _ID_ for a MOSFET can be written (using the gradual channel approximation) as

I_{D,Sat} = frac{W}{L} mu, C_{inv}frac{(V_{G}-V_{th})^2}{2}

Where

  • _W_ is the width of the transistor channel
  • _L_ is the channel length
  • μ is the channel carrier mobility (assumed constant here)
  • Cinv is the capacitance density associated with the gate dielectric when the underlying channel is in the inverted state
  • _VG_ is the voltage applied to the transistor gate
  • _VD_ is the voltage applied to the transistor drain
  • Vth is the threshold voltage

The term VG − Vth is limited in range due to reliability and room temperature operation constraints, since a too large _VG_ would create an undesirable, high electric field across the oxide. Furthermore, Vth cannot easily be reduced below about 200 mV, because leakage currents due to increased oxide leakage (that is, assuming high-κ dielectrics are not available) and subthreshold conduction raise stand-by power consumption to unacceptable levels. (See the industry roadmap,[1] which limits threshold to 200 mV, and Roy et al. [2]). Thus, according to this simplified list of factors, an increased ID,sat requires a reduction in the channel length or an increase in the gate dielectric capacitance.

Materials and considerations

Replacing the silicon dioxide gate dielectric with another material adds complexity to the manufacturing process. Silicon dioxide can be formed by oxidizing the underlying silicon, ensuring a uniform, conformal oxide and high interface quality. As a consequence, development efforts have focused on finding a material with a requisitely high dielectric constant that can be easily integrated into a manufacturing process. Other key considerations include band alignment to silicon (which may alter leakage current), film morphology, thermal stability, maintenance of a high mobility of charge carriers in the channel and minimization of electrical defects in the film/interface. Materials which have received considerable attention are hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, typically deposited using atomic layer deposition. It is expected that defect states in the high-k dielectric can influence its electrical properties. Defect states can be measured for example by using zero-bias thermally stimulated current, zero-temperature-gradient zero-bias thermally stimulated current spectroscopy,[3][4] or inelastic electron tunneling spectroscopy (IETS).

Use in industry

The industry has employed oxynitride gate dielectrics since the 1990s, wherein a conventionally formed silicon oxide dielectric is infused with a small amount of nitrogen. The nitride content subtly raises the dielectric constant and is thought to offer other advantages, such as resistance against dopant diffusion through the gate dielectric. In early 2007, Intel announced the deployment of hafnium-based high-k dielectrics in conjunction with a metallic gate for components built on 45 nanometer technologies, and has shipped it in the 2007 processor series codenamed Penryn “Penryn (microarchitecture)”).[5][6] At the same time, IBM announced plans to transition to high-k materials, also hafnium-based, for some products in 2008. While not identified, the most likely dielectric used in such applications are some form of nitrided hafnium silicates (HfSiON). HfO2 and HfSiO are susceptible to crystallization during dopant activation annealing. NEC Electronics has also announced the use of a HfSiON dielectric in their 55 nm _UltimateLowPower_technology.[7] However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. This leakage effect becomes more severe as hafnium concentration increases. There is no guarantee however, that hafnium will serve as a de facto basis for future high-k dielectrics. The 2006 ITRSroadmap predicted the implementation of high-k materials to be commonplace in the industry by 2010.

最快时钟频率 不忘初心,方得始终

评论

Your browser is out-of-date!

Update your browser to view this website correctly. Update my browser now

×